Sasken - Engineer - Design Recruitment

Role Description: Individual contributer in a team as Jr. verification Engineer:          Responsible for developing BFMs, testcases, verification of Ips/SoC 


Desired Profile Mandatory Skills: 

• Good acadamic record 
• Good Digital fundamentals/Electronics fundamentals 
• Good understanding of VLSI flow, testbench development proficient in C/C++/Verilog/VHDL languages 
• Good fundamentals in Microcontroler architecture( 8085) Experience in verification  

Desired Skills : 

• Experience any of the following standards is desirable Gate level simulation and 
• Good debugging skills 

Experience 0 - 3 Years 


Industry Type Telcom/ISP Role Database Architect/Designer 


Functional Area Embedded/EDA /VLSI/ASIC/Chip Design 


Education UG - B.Tech/B.E. - Computers PG - Any PG Course 


Location Bengaluru/Bangalore 


Keywords IC Design, C, C++, Verilog, VHDL 


Contact
HR 
Sasken Communication Technologies Ltd 


Website
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